Stacked and Doherty Power Amplifier for 6G Communication Deployment

Abstract

This paper presents a fully integrated stacked architecture to address the challenges of 6G application using CMOS analog pre-distortion and tunable neutralization techniques. By using this method for the stacked power amplifier design, a baseband and passband impedance transformation is achieved, that combined with the stacked power amplifier architecture allows for high efficiency in deep back off, with a reduced load modulation for high bandwidth. This project designs an efficient Stacked Power Amplifier (PA) for 6G. The power amplifier is implemented in 180nm CMOS technology using Cadence and ADS tool. The usage of a diode pre-distorter for analog pre-distortion is investigated for the stacked power amplifier design. It is shown that the linearity of the stacked power amplifier has been significantly improved compared to a bipolar transistor at almost no additional layout size. This research work presents design of a Ka band power amplifier for sixth generation (6G) mobile communication in CMOS design. The stacked power amplifier consists of two different stages of architecture. With 5-volt supply, the stacked power amplifier achieves a small-signal gain of 16 dB, saturated output power (P_sat) of 18 dBm, and achieves the maximum power added efficiency of 34.79%. The amplifier has been designed in 180-nm CMOS technology.